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EL9110
Data Sheet November 30, 2007 FN7305.5
Differential Receiver/Equalizer
The EL9110 is a single channel differential receiver and equalizer. It contains a high speed differential receiver with 5 programmable poles. The outputs of these pole blocks are then summed into an output buffer. The equalization length is set with the voltage on a single pin. The EL9110 also contains a three-statable output, enabling multiple devices to be connected in parallel and used in a multiplexing application. The gain can be adjusted up or down by 6dB using the VGAIN control signal. In addition, a further 6dB of gain can be switched in to provide a matched drive into a cable. The EL9110 has a bandwidth of 150MHz and consumes just 33mA on 5V supply. A single input voltage is used to set the compensation levels for the required length of cable. The EL9110 is available in the 16 Ld QSOP package and is specified for operation over the full -40C to +85C temperature range.
Features
* 150MHz -3dB bandwidth * CAT-5 compensation - 75MHz @ 1000ft - 125MHz @ 500ft * 33mA supply current * Differential input range 3.2V * Common mode input range 4.5V * 5V supply * Output to within 1.5V of supplies * Available in 16 Ld QSOP package * Pb-free available (RoHS compliant)
Applications
* Twisted-pair receiving/equalizer * KVM (Keyboard/Video/Mouse)
Ordering Information
PART NUMBER EL9110IU EL9110IU-T7* EL9110IU-T13* EL9110IUZ (Note) EL9110IUZ-T7* (Note) PART MARKING 9110IU 9110IU 9110IU 9110IUZ 9110IUZ PACKAGE 16 Ld QSOP 16 Ld QSOP 16 Ld QSOP 16 Ld QSOP (Pb-free) 16 Ld QSOP (Pb-free) 16 Ld QSOP (Pb-free) PKG. DWG. # MDP0040 MDP0040 MDP0040 MDP0040
* VGA over twisted-pair * Security video
Pinout
EL9110 (16 LD QSOP) TOP VIEW
CTRL_REF 1 16 CMEXT 15 VS+ 14 ENBL 13 VSA+ 12 VOUT 11 VSA10 0V 9 X2
MDP0040 MDP0040
VCTRL 2 VINP 3 VINM 4 VS- 5 CMOUT 6 VGAIN 7 LOGIC_REF 8
EL9110IUZ-T13* 9110IUZ (Note)
*Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003, 2005, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL9110
Absolute Maximum Ratings (TA = +25C)
Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . . .12V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.5V to VS+ +0.5V
Thermal Information
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Die Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER AC PERFORMANCE BW SR THD Bandwidth Slew Rate
VSA+ = VA+ = +5V, VSA- = VA- = -5V, TA = +25C, Unless Otherwise Specified CONDITIONS MIN (Note 1) TYP MAX (Note 1) UNIT
DESCRIPTION
(See Figure 1) VIN = -1V to +1V, VG = 0.35, VC = 0, RL = 75 + 75 10MHz 1VP-P out, VG = 0.35V, X2 gain, VC = 0
150 1.5 -50
MHz V/ns dBc
Total Harmonic Distortion
DC PERFORMANCE VOS Offset Voltage (bin #1) Offset Voltage (bin #2) INPUT CHARACTERISTICS CMIR CMIRx ONOISE CMRR CMRR+ CMBW CMSLEW CINDIFF RINDIFF CINCM RINCM +IIN -IIN VINDIFF Common-mode Input Range Extended CMIR Output Noise Common-mode Rejection Ratio Common-mode Rejection Ratio CM Amplifier Bandwidth CM Slew Rate Differential Input Capacitance Differential Input Resistance CM Input Capacitance CM Input Resistance Positive Input Current Negative Input Current Differential Input Range Common-mode extension off Common-mode extension on VG = 0.35, X2 gain, 75 + 75 load, VC = 0.6 Measured at 10kHz Measured at 10MHz 10K || 10pF load Measured @ +1V to -1V Capacitance VINP to VINM Resistance VINP to VINM Capacitance VINP = VINM to ground Resistance VINP = VINM to ground DC bias @ VINP = VINM = 0V DC bias @ VINP = VINM = 0V VINP - VINM when slope gain falls to 0.9 2.5 1 1 -4/+3.5 4.5 25 60 50 50 100 600 2.4 1.2 2.8 1 1 3.2 V V mV RMS dB dB MHz V/s fF M pF M A A V X2 gain, no equalization -250 -10 CPI9049 +250 mV mV
OUTPUT CHARACTERISTICS VO IOUT ROUTCM DiffGain SUPPLY ISON ISOFF Supply Current Supply Current VENBL = 5, VINM = 0 VENBL = 0, VINM = 0 27 0.4 38 0.8 mA mA Output Voltage Swing Output Drive Current CM Output Resistance Differential Gain RL = 150 RL = 10, VINP = 1V, VINM = 0V, X2 = gain, VG = 0.35 at 100kHz VC = 0, VG = 0.35, X2 = 5, RL = 75 + 75 0.85 50 3.5 60 30 1.0 1.1 V mA
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FN7305.5 November 30, 2007
EL9110
Electrical Specifications
PARAMETER PSRR VSA+ = VA+ = +5V, VSA- = VA- = -5V, TA = +25C, Unless Otherwise Specified (Continued) CONDITIONS DC to 100kHz, 5V supply MIN (Note 1) TYP 60 MAX (Note 1) UNIT dB
DESCRIPTION Power Supply Rejection Ratio
LOGIC CONTROL PINS VHI VLOW ILOGICH ILOGICL NOTE: 1. Parts are 100% tested at +25C. Over-temperature limits established by characterization and are not production tested. Logic High Level Logic Low Level Logic High Input Current Logic Low Input Current VIN - VLOGIC ref for guaranteed high level VIN - VLOGIC ref for guaranteed low level VIN = 5V, VLOGIC = 0V VIN = 0V, VLOGIC = 0V 1.35 0.8 50 15 V V A A
Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN NAME CTRL_REF VCTRL VINP VINM VSCMOUT VGAIN LOGIC_REF X2 0V VSAVOUT VSA+ ENBL VS+ CMEXT Power Output Power Logic Input Power Logic Input PIN TYPE Input Input Input Input Power Output Input Input Logic Input PIN FUNCTION Reference voltage for VGAIN and VCTRL pins Control voltage (0 to 1V) to set equalization Positive differential input Negative differential input -5V to core of chip Output of common mode voltage present at inputs Control voltage to set overall gain (0V to 1V) Reference voltage for all logic signals Logic signal; low - gain = 1, high - gain = 2 0V reference for output voltage -5V to output buffer Single-ended output voltage reference to pin 10 +5V to output buffer Logic signal to enable pin; low - disabled, high - enabled +5V to core of chip Logic signal to enable CM range extension; active high
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FN7305.5 November 30, 2007
EL9110 Typical Performance Curves
5 3 GAIN (dB) 1 -1 -3 -5 1M VGAIN = 0V VCTRL = 0V RLOAD = 150 X2 = OFF THD (dBc) -40 -45 -50 -55 -60 -65 0.1M VGAIN = 0V VCTRL = 0V VSS = +5V VEE = -5V RLOAD = 150 X2 = OFF INPUT = 0dBm
10M FREQUENCY (Hz)
100M
1M
10M
100M
FREQUENCY (Hz)
FIGURE 1. FREQUENCY RESPONSE
FIGURE 2. TOTAL HARMONIC DISTORTION
0 200mV/DIV -20 CMRR (dBc) -40 -60 -80 -100 100k VCTR = 0V VGAIN = 0.35V X2 = ON
2ns/DIV
1M
10M
100M
FREQUENCY (Hz)
FIGURE 3. RISE TIME
FIGURE 4. COMMON MODE REJECTION
4 2 GAIN (dB) 0 -2 -4 -6 100k VGAIN = 0.35V VCTRL = 0V RLOAD = 150 X2 = ON -PSRR (dB)
-20 -40 -60 -80 -100 -120 10
VEE = -5V VCTRL = 0V VGAIN = 0V INPUTS ON GND
1M
10M
100M
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 5. CM AMPLIFIER BANDWIDTH
FIGURE 6. PSRR vs FREQUENCY
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FN7305.5 November 30, 2007
EL9110 Typical Performance Curves (Continued)
0 -20 +PSRR (dB) -40 -60 -80 -100 10 VCC = 5V VCTRL = 0V VGAIN = 0V INPUTS ON GND GAIN (dB) 60 50 40 30 20 10 0 -10 -20 100 1k 10k 100k 1M 10M 100M 1M 100mV STEP 10M FREQUENCY (Hz) VCTRL = 0mV 100M VCTR = 800mV 10dB/DIV
FREQUENCY (Hz)
FIGURE 7. PSRR vs FREQUENCY
FIGURE 8. GAIN AS THE FUNCTION OF VCTRL
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 50 10ns/DIV GROUP DELAY (ns) 30 10 -10 -30 -50 1M VCTRL = 0mV POWER DISSIPATION (W) 1.2 1 0.8 0.6 0.4 0.2 0 10M FREQUENCY (Hz) 100M 200M 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) 791mW
J QS OP 16 58 C /W
1.4
A =1
VCTRL = 900mV 100mV STEP
FIGURE 9. GROUP DELAY AS THE FUNCTION OF THE FREQUENCY REPONSE CONTROL VOLTAGE (VCTRL)
FIGURE 10. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.8 POWER DISSIPATION (W) 1.6 1.4 1.2 1.116W 1 0.8 0.6 0.4 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C)
J QS
A =1
OP 16 12 C /W
FIGURE 11. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
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FN7305.5 November 30, 2007
EL9110 Applications Information
Logic Control
The EL9110 has three logical input pins, Chip Enable (ENBL), Common Mode Extend (CMEXT), and Switch Gain (X2). The logic circuits all have a nominal threshold of 1.1V above the potential of the logic reference pin. In most applications it is expected that this chip will run from a +5V, 0V, -5V supply system with logic being run between 0V and +5V. In this case the logic reference voltage should be tied to the 0V supply. If the logic is referenced to the -5V rail, then the logic reference should be connected to -5V. The logic reference pin sources about 60A and this will rise to about 200A if all inputs are true (positive). The logic inputs all source up to 10A when they are held at the logic reference level. When taken positive, the inputs sink a current dependent on the high level, up to 50A for a high level 5V above the reference level. The logic inputs, if not used, should be tied to the appropriate voltage in order to define their state. differential signal and maintain the amplifier within its common mode operating range. This operation may not always be desirable. A problem occurs because the EL9110 sinks or sources a common mode current though its input pins to create the common mode offset voltage. Assuming the system has been set up so that the differential line has a well-balanced impedance, then a problem will only occur when the common mode impedance to ground is not low. This will occur in systems where the inputs to the EL9110 are AC coupled. In such systems it is recommended that the common mode extension be disabled. In systems where the differential input signal is directly coupled and has its common mode level defined by a low impedance line driver, the common mode extension circuitry can extend the total common mode range by 2V to 3V.
Equalizing
When transmitting a signal across a twisted pair cable, it is found that the high frequency (above 1MHz) information is attenuated more significantly than the information at low frequencies. The attenuation is predominantly due to resistive skin effect losses and has a loss curve which depends on the resistivity of the conductor, surface condition of the wire and the wire diameter. For the range of high performance twisted pair cables based on 24awg copper wire (Cat 5 etc.) these parameters vary only a little between cable types, and in general cables exhibit the same frequency dependence of loss. (The lower loss cables can be compared with somewhat longer lengths of their more lossy brothers.) This enables a single equalizing law equation to be built into the EL9110. With a control voltage applied between pins 2 and 1, the frequency dependence of the equalization is shown in Figure 8. The equalization matches the cable loss up to about 100MHz. Above this, system gain is rolled off rapidly to reduce noise bandwidth. The roll-off occurs more rapidly for higher control voltages, thus the system (cable + equalizer) bandwidth reduces as the cable length increases. This is desirable, as noise becomes an increasing issue as the equalization increases. The cable loss for 100m, 200m, and 300m of CAT 5 cable, based on manufacturer's loss curves is shown in Figure 14. Thus: * 100m requires VC = 0.2V * 200m requires VC = 0.6V and: * 300m requires VC = 1.0V approximately
Control Reference and Signal Reference
Analog control voltages are required to set the equalizer and contrast levels. These signals are voltages in the range 0V to 1V, which are referenced to the control reference pin. It is expected that the control reference pin will be tied to 0V and the control voltage will vary from 0V to 1V. It is; however, acceptable to connect the control reference to any potential between -5V and 0V to which the control voltages are referenced. The control voltage pins themselves are high impedance. The control reference pin will source between 0A and 200A depending on the control voltages being applied. The control reference and logic reference effectively remove the necessity for the 0V rail and operation from 5V (or 0V and 10V) only is possible. However we still need a further reference to define the 0V level of the single ended output signal. The reference for the output signal is provided by the 0V pin. The output stage cannot pull fully up or down to either supply so it is important that the reference is positioned to allow full output swing. The 0V reference should be tied to a 'quiet ground' as any noise on this pin is transferred directly to the output. The 0V pin is a high impedance pin and draws dc bias currents of a few A and similar levels of AC current.
Common Mode Extension
The common mode extension circuitry extends the range of input common mode voltage before the input differential amplifier is overloaded. It does this by reducing the voltage equally at both inputs of the first differential amplifier as the common mode signal rises towards the supply. Similarly, when the common mode input signal goes low, the inputs to the first differential amplifier are raised whilst preserving the
Contrast
By varying the voltage between pins 7 and 1, the gain of the signal path can be changed in the ratio 4:1. The gain change varies almost linearly with control voltage. For normal
FN7305.5 November 30, 2007
6
EL9110
operation it is anticipated the X2 mode will be selected and the output load will be back matched. A unity gain to the output load will then be achieved with a gain control voltage of about 0.35V. This allows the gain to be trimmed up or down by 6dB to compensate for any gain/loss errors that affect the contrast of the video signal. Figure 12 shows an example plot of the gain to the load with gain control voltage.
2.0 1.8 1.6 GAIN (V) 1.4 1.2 1.0 0.8 0.6 0.4 0 0.2 0.4 VGAIN 0.6 0.8 1.0
Circuit and Layout Recommendation
The interconnection cable is a transmission line therefore for proper function it should be treated like transmission line, a refection-free termination is necessary. A reflection-free termination is a real "ohmic" resistor with as less as possible reactive parasitic. The traces of the layout, up to the point where of the termination resistor placed, are part of the transmission line which also includes the cable's connector. A connector with a better controlled impedance is an obligation for good picture quality. The termination resistor should be placed close to the inputs of the device's pins (pin 3 and pin 4.) The small capacitance differential and common mode capacitance of the input pins of the device makes it possible to connect parallel to the termination resistor. The cable will work as an antenna for all the RF spectrum which is "in the air" where the cable is used. The spectrum, particularly its common mode components, could and will contain high energy level of transients which are above the built-in protection level of the device and easily could damage its inputs. Using a transient protection circuit according to the given application is recommended. Since the used signal's bandwidth is in the range of 100MHz, for layout and power supply bypassing the roles of RF design should be applied.
FIGURE 12. VARIATION OF GAIN WITH GAIN CONTROL VOLTAGE
70 60 ATTENUATION (dB) 50 40 200M 30 20 10 0 0.01M 100M 50M 300M
The following picture is taken from the DB9110 demoboard's layout. For better visibility the ground plain is removed. The ground plane is shown in Figure 14.
0.10M
1M FREQUENCY (Hz)
10M
100M
FIGURE 13. CAT-5 CABLE ATTENUATION CHARACTERISTICS
FIGURE 14. DEMO BOARD LAYOUT
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FN7305.5 November 30, 2007
EL9110
The accompanying circuit diagram is shown in Figure 15.
R11 330 C5 1F 1 CTRL CMEXT 16 _REF 2 VCTRL R6 3 VINP R5 R7 R9 4 VINM 5 VSTP7 6 CMOUT R12 330 C10 1F 7 VGAIN LOGIC 8 _REF VSA- 11 0V 10 X2 9 C11 1nF VSA+ 13 VOUT 12 ENBL 14 VS+ 15
C7 1F
C6 1nF
C8 1nF
C9 1F
FIGURE 15. CIRCUIT DIAGRAM
Block Diagram
CMEXT CMOUT VS+ VS-
COMMON MODE RANGE EXTENDED COMMON MODE RECOVERY INPUT AMP
BIAS CIRCUITRY
LOGICREF X2
LOW FREQ BOOST X2/X1 CONTRAST + EQUALIZING BOOST 6dB RANGE DIFFERENTIAL TO SINGLE-ENDED CONTROL ASP GAIN ASP VSA+ ENBL VOUT 0V VSA-
DIFFERENTIAL LINE IN VINP VINM
VCTRL
CTRLREF
VGAIN VS- & VSA- connected to -5V -5V CONNECTED TO CONNECTED TO VS+ & VSA+ connected to +5V+5V
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FN7305.5 November 30, 2007
EL9110 Typical Application
VCTRL 0.1F 1 CTRL CMEXT 16 _REF 2 VCTRL 3 VINP 100 4 VINM -5V 0.1F CMOUT +5V 5 VS6 CMOUT 7 VGAIN LOGIC 8 _REF VSA+ 13 VOUT 12 75 VSA- 11 0V 10 X2 9 +5V -5V 0.1F VS+ 15 ENBL 14 +5V
0.1F
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FN7305.5 November 30, 2007
EL9110 Quarter Size Outline Plastic Packages Family (QSOP)
A D N (N/2)+1
MDP0040
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY INCHES SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES
PIN #1 I.D. MARK
A A1 A2 b
0.068 0.006 0.056 0.010 0.008 0.193 0.236 0.154 0.025 0.025 0.041 16
0.068 0.006 0.056 0.010 0.008 0.341 0.236 0.154 0.025 0.025 0.041 24
0.068 0.006 0.056 0.010 0.008 0.390 0.236 0.154 0.025 0.025 0.041 28
Max. 0.002 0.004 0.002 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference
1, 3 2, 3 Rev. F 2/07
E
E1
1 B 0.010 CAB
(N/2)
c D E
e C SEATING PLANE 0.004 C 0.007 CAB b
H
E1 e L L1 N
L1 A c SEE DETAIL "X"
NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.010 A2 GAUGE PLANE L 44 DETAIL X
A1
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 10
FN7305.5 November 30, 2007

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